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Against popular believe the sound quality of a failing digital connection first starts degrading before the connection generate glitches or stops working all together. Whether the degradation is audible depends on the quality of the equipment used and to a certain extend to the listener’s qualities. But how can a signal that only carries ones and zeros go just a bit wrong, pun intended. To explain this, I will take the AES-3 family data stream as an example, but about the same applies to any other digital audio connection.


Digital signals start out as square waves looking like this:


Basic bit patern


In all four AES-3 versions this basic square wave is in fact the clock signal and the ‘Zero’ at the same time. ‘Ones’ are formed by a square wave of double the frequency. By alternating between square waves of either frequencies both ones and zeros can be sent. This is how such signal would look like, with the clock cycles indicated by the dotted vertical lines.


Bit patern 


Whether a zero or one is sent, can be seen by looking for a polarity change within a clock cycle. Looking at the first cycle we see the signal being high during the entire cycle, there is no change in polarity, meaning it is a zero. The second cycle has a transition from low to high halfway the clock cycle and therefore is a one. It also could have been a transition from high to low, it’s the polarity change within the cycle that counts. The third cycle remains low, so no polarity change, thus a zero. The fourth cycle remains high. Again no polarity change within the clock cycle thus a zero. The fifth cycle goes from low to high halfway, so it’s a one.


Correct detection of bit values 


Unfortunately, square waves as drawn here can not exist in a real world, since that would require unlimited bandwidth. Normally square waves are more or less distorted and under bad conditions might end up looking more like this. 


Still that’s no problem as long as the distortion is within limits, like here. The input circuit of the d/a-converter looks at certain points within the clock signal to determine whether the signal is high or low. As long as the signal remains within specifications, it will still work without errors as can be seen here.


Correct detection of the bit patern 


But it is a signal that requires a lot of bandwidth and as little interference as possible. The use of a poor quality cable, the presence of a ground loop or other mishap can easily mutilate the signal like this.


Heavily distorted square wave 


At first this might not look that much different from the other signal I showed, but let’s see how the input circuit of the d/a-converter interprets it.


Detection error due to distorted square wave 


The first measurement within the first clock cycle reads a positive, but only just. The second measurement is also positive so the result must be a zero. The second clock cycle starts with a ‘very low’, that will be interpreted as a low, and a high. Since there is a transition within the clock cycle, it is a one. The third cycle shows a low and again a very low that will be read as a low. Two lows within the clock cycle means a zero. The fourth cycle shows a low and a high, resulting in a one and the fifth cycle shows a low and a high as well, again resulting in a 1. Now let’s compare this to the original signal and you will see that the fourth clock cycle should have been a zero instead of a one. Since digital information is protected by error correction schemes, the error correction will easily correct this one error. But I have only drawn five clock cycles here, as where a signal at cd-quality runs at over 1.4 million bits per second and thus requires 1.4 million clock cycles on the bus. The power of the error correction is limited by the design of the error correction scheme and by computing power of the electronics in the d/a-converter. At it’s limits this might delay the throughput and thus cause jitter. Beyond its limits interpolation is used to ‘repair’ missing bits. And if that’s not enough, the distortion of the square wave makes it hard for the input circuitry of the d/a-converter to detect the correct clock timing. This can also cause jitter.


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